Scan compression Insights

What is Scan compression?

Scan compression is a technique used in integrated circuit testing to reduce the amount of test data and the test application time. It involves modifying the scan chains in a design to minimize the number of scan flip-flops that need to be controlled and observed during testing. This is achieved by encoding the test vectors, which significantly reduces the size of the test data that needs to be stored and applied. This also decreases the time required to apply the test, leading to lower testing costs.

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What other technologies are related to Scan compression?

Scan compression Competitor Technologies

Logic BIST

Logic BIST (Built-In Self-Test) is an alternative DFT (Design-for-Test) technique to scan compression for testing logic. They both aim to achieve similar goals, so they can be considered as alternatives.

mentioned alongside Scan compression in 19% (55) of relevant job posts

Scan compression Complementary Technologies

fault simulation

Fault simulation is used to evaluate the effectiveness of scan compression techniques by determining fault coverage. Higher fault coverage after scan compression is a desired goal.

mentioned alongside Scan compression in 43% (62) of relevant job posts

ATPG

Automatic Test Pattern Generation (ATPG) tools generate test patterns that are used with scan compression to detect faults. Scan compression helps to reduce the size and number of test patterns that ATPG tools need to generate.

mentioned alongside Scan compression in 10% (168) of relevant job posts

JTAG

JTAG is a standard for accessing internal test structures, and is often used to interface with scan chains that implement scan compression to get data in and out of the chip.

mentioned alongside Scan compression in 1% (101) of relevant job posts