Physical Verification

What is Physical Verification?

Physical verification is a crucial stage in the integrated circuit (IC) design flow that ensures the manufactured chip accurately reflects the intended design and meets all manufacturing requirements. It involves a series of checks performed on the final layout database, including design rule checking (DRC), layout vs. schematic (LVS), and electrical rule checking (ERC). DRC verifies that the layout adheres to the manufacturing process rules to ensure manufacturability and reliability. LVS compares the layout's connectivity and device sizes with the schematic to guarantee functional correctness. ERC checks for electrical issues like shorts, opens, and excessive current density. Failing these checks can lead to non-functional chips or reduced yields, making physical verification an indispensable step before tapeout.